module top_module (
    input [3:1] y,
    input w,
    output Y2);

    `define STT_W 3
    `define STT_W1 `STT_W - 1

    wire [`STT_W1:0]   state = y;
    reg [`STT_W1:0]   nxt_state;

    localparam sA  = `STT_W'd0;
    localparam sB  = `STT_W'd1;
    localparam sC  = `STT_W'd2;
    localparam sD  = `STT_W'd3;
    localparam sE  = `STT_W'd4;
    localparam sF  = `STT_W'd5;

    // State transition logic (combinational)
    always @(*) begin
        case (state)
            sA:begin
                if(w)
                    nxt_state = sA;
                else
                    nxt_state = sB;
            end
            sB:begin
                if(w)
                    nxt_state = sD;
                else
                    nxt_state = sC;
            end
            sC:begin
                if(w)
                    nxt_state = sD;
                else
                    nxt_state = sE;
            end
            sD:begin
                if(w)
                    nxt_state = sA;
                else
                    nxt_state = sF;
            end
            sE:begin
                if(w)
                    nxt_state = sD;
                else
                    nxt_state = sE;
            end
            sF:begin
                if(w)
                    nxt_state = sD;
                else
                    nxt_state = sC;
            end
          default: begin
            nxt_state = sA;
          end
        endcase
    end
 
    assign  Y2   =   nxt_state[1];

endmodule
